Abstract:
The increasing cost of building, operating, managing, and maintaining state-of-the-art silicon manufacturing facilities has pushed several stages of the semiconductor device’s manufacturing supply chain offshore. However, many of these offshore facilities are identified as untrusted entities. Processing and fabrication of ICs in an untrusted supply chain poses a number of challenging security threats such as IC overproduction, Trojan insertion, Reverse Engineering, Intellectual Property (IP) theft, and counterfeiting.
To counter these threats, various hardware design-for-trust techniques have been pro- posed. Logic locking, as a proactive technique among these techniques, has been introduced as a technique that obfuscates and conceals the functionality of IC/IP using additional key inputs that are driven by an on-chip tamper-proof memory.
Shortly after introducing the primitive logic locking solutions, a very strong Boolean attack, the Satisfiability (SAT) attack. It was shown that the SAT attack could break all previously proposed primitive locking mechanisms in almost polynomial time. To thwart the strength of SAT attack, researchers have investigated many directions, such as formulating locking solutions that significantly increase the number of required SAT iterations, or formulating the locking solutions such that it is not translatable to a SAT problem.
However, further investigations demonstrated that some of these locking techniques are vulnerable to other types of attacks such as Signal Probability Skew (SPS) attack, removal attack, approximate-based attack(s), bypass attack, and Satisfiability Module Theories (SMT) attack. In addition, these techniques suffer from very low output corruption. Hence, an unactivated IC behaves almost identical to an unlocked IC with exception of one or few inputs.
