Abstract:
Field-Programmable Gate Arrays (FPGA) are powerful processing platforms to
support an efficient processing for a diverse range of applications. Recently, High-
Level Synthesis (HLS) tools emerged and shifted the paradigm of hardware design and
made the process of mapping high-level programming languages to hardware design
such as C to VHDL/Verilog feasible. HLS tools offer many techniques to optimize
designs for both area and performance, but resource usage and timing reports of
HLS tools mostly deviate from post-implementation results. In addition, to evaluate
a hardware design performance, it is critical to determine the maximum achievable
clock frequency. Obtaining such information using static timing analysis provided
by CAD tools is difficult, due to the multitude of tool options. Moreover, a binary
search to find the maximum frequency is tedious, time-consuming, and often does
not obtain the optimal result. To address these challenges, this thesis proposes a
framework, called Pyramid, that uses machine learning to accurately estimate the
optimal performance and resource utilization of an HLS design. For this purpose,
first a database of C-to-FPGA results from a diverse set of benchmarks was created.
To find the achievable maximum clock frequency, Minerva was used, which is
an automated hardware optimization tool. Minerva determines the close-to-optimal
settings of tools, using static timing analysis and a heuristic algorithm, and targets
either optimal throughput or optimal throughput-to-area. Pyramid uses the database
to train an ensemble machine learning model to map the HLS-reported features to the
results of Minerva. To this end, Pyramid re-calibrates the results of HLS's report in
order to bridge the accuracy gap, and enables developers to estimate the throughput
or throughput-to-area of a hardware design by more than 95% accuracy, without
performing the actual implementation process.
