Abstract:
To prevent setup and hold failures during the operation of a chip, different sources of on chip variability need to be modeled and margined during the physical design. One of the sources of the variability is dynamic IR drop and cycle to cycle voltage variation. The excessive IR drop or large cycle to cycle voltage variation could cause various forms of timing failure. In this thesis, we present a novel technique for reducing the dynamic IR-drop by leveraging available timing slacks and scheduling useful skews. Unlike previous work, which is focused on reducing the peak current, we breakdown the peak current minimization problem into many smaller problems of reducing the intensity of individual hot spots. In addition to timing information, the power delivery network, floorplan, and cell placement information are considered while scheduling the clock arrival times. This technique reduces the peak dynamic IR-drop by ~50%, peak current by ~30% and cycle to cycle voltage variation by more than 30%.
