Design, Implementation and Analysis of Efficient FPGA Based Physical Unclonable Functions

Abstract

With the advent of Internet of Things (IoTs), secure communication between devices is a big challenge. Billions of new devices and sensors are going to be connected to internet. To ensure secure communication with the devices we need hardware primitives that are well suited to the requirements of IoTs. Recent research has led to an increased interest in security measures, especially in solutions that are physically unique and unclonable. Physical Unclonable Function (PUF) has been found to be a strong candidate for this purpose. Since PUF extracts the inherent manufacturing variations of a hardware chip, therefore it can be used as a finger print of devices. Eventually these finger prints can be used to authenticate devices and also to generate secure keys for cryptographic functions. This thesis describes the development of efficient and reliable PUF for FPGAs. Novel PUFs have been designed for this purpose. Furthermore, it also covers the generation and analysis of PUF responses in a more coherent and systematic method. For the generation of PUF responses different bit-generation schemes have been used and their results have been compared with each other. This novel study was done to determine the best scheme among the most popular schemes developed so far by different researchers. Software scripts were developed for all the schemes. Similarly, for the analysis, new metrics have been presented for the evaluation of PUF responses. Additionally, software scripts have been developed for analysis of PUF responses. These scripts can be applied to any type of PUF.

Design, development, implementation and testing of two major types of PUF have been carried out. One is a memory based PUF: SR-Latch based design. The second is a delay based PUF: Ring oscillator based design. Both designs have been thoroughly tested on FPGA devices. Performance metrics of both designs have been presented and compared to the state of the art PUFs. Experiments were carried out on different FPGA technologies. It was done to prove the applicability and portability of our designs.

One of the major requirements of PUF intended for IoT applications is that the device area must be efficiently utilized. The current state of the art PUFs are expensive for low area implementation. Therefore, in this work a highly efficient PUF has been developed and tested for FPGAs. Additionally, the PUF is very reliable for use at different environmental conditions. It makes it further attractive because the device can be used in broad range of temperature and voltage variations. To regenerate the same PUF response under different conditions we used the error correction scheme. We also presented different schemes that are suitable from the security point of view.

Lastly we presented a prototype of an efficient SR-Latch based PUF design, with two times improvement in area over the state of the art, thus making it very attractive for low-area designs. This PUF is able to reliably generate a 128-bit cryptographic key.